Digital Equipment Corporation (DEC) PDP-1 and PiDP-1 Computer System Information

Numbering Systems

Numbering Systems are named after the Latin for their bases. Our numbering system is base ten (10) therefore it is the Decimal numbering system and uses the Digits 0 through 9. For Numbering Systems with smaller bases such as Binary or Octal we just use a smaller range of Digits. For Bases larger than Decimal then Letters are used to provide the extra Digits. Some examples of Numbering System are:-

The Latin naming convention of Sexadecimal for Base 16 was unacceptable so renamed to Hexadecimal, abbreviated as Hex. For binary computers the Base 8 (Octal) and Base 16 (Hexadecimal) are significant as they permit the simple representation of binary numbers with fewer Digits.

The catch is a number such as 1010 is a valid number in all these Number Systems but represents different values when converted. If 10010 is a Binary Number then this is 22 in Octal, 18 Decimal or 12 Hex. As 10010 is a valid Hex number this converts to 1000000000010000 Binary (i.e. 0001-0000-0000-0001-0000) or 200020 Octal (i.e. 010-000-000-000-010-000). As the same number in each of these Bases can convert to a different value in other Bases the applicable Base for a number has to be stated to avoid confusion. So a shorthand is to add a prefix applicable to indicate the Base to avoid confusion:-

• 0b Binary
• 0o Octal
• 0x Hex

Unless otherwise stated, by convention a number without a prefix is a Decimal number.

Computers have been designed using different Bases, for example:-

• Binary Computers - PDP-1. PDP-11, VAX-11/780
• Ternary Computers - Setun, Setun-70, QTC-1
• Decimal Computers - ENIAC, IBM 650, IBM 7070

Bits

Short for Binary Digit, a Bit represents the basic unit of information in a binary, digital computer. This represents one of two possible states such as:

• On or Off
• True or False
• ONE (1) or ZERO (0)

In this document there are three (3) forms when grouping Bits:-

• n-Bits will describe the size of a binary number. For example 18-Bits is the number of Bits in a PDP-1 Word.
• Bit-n will describe the position of a single Bit within a binary number. For example Bit-5 specifies the location of the Indirect Bit in a PDP-1 instruction.
• Bits-nn:nn will describe a group or field of bits within a larger binary entity. For example in a PDP-1 instruction Bits-0:5 contains the opcode while Bits-6:17 may contain a memory address.

The above example has Bits-0:4 labelled as the Opcopde field, Bit-5 as the Indirect Bit and Bits-6:17 as the Memory Address field. Therefore this specifies the format of an 18-Bit PDP-1 instruction.

Bytes

A Byte is typically the smallest addressable binary unit and that has usually been the number of bits to contain one text character. These days people tend to assume a Byte is always 8-Bits but that has not always been the case:-

1. 6-Bits:- DEC PDP-1, PDP-4, PDP-7, etc.
2. 7-Bits:- DEC PDP-10, IBM 1401, etc.
3. 8-Bits:- IBM 360 (EBCDIC)
4. 9-Bits:- Sperry 11/2200 (9-Bit ASCII)

The PDP-1 central processors using 6-Bit Bytes could pack three (3) 6-Bit Bytes into one (1) 18-Bit Word. At the other extreme the Control Data Cyber 6600 could pack ten (10) 6-Bit characters into their 60-Bit Words.

Characters

In this period 6-Bit Binary-coded Decimal (BCD) character sets were common for encoding text for computers. There was minimal standardisation with each manufacturer independently creating internal computer codes for characters. The PDP-1 used a 6-Bit character set known as Concise Code (CIO) for text.

Punch Card Codes

In 1949 IBM introduced the IBM 026 printing keypunch which was using a 6-Bit, 64 character code. The 8-Bit, IBM 029 printing keypunch was not introduced until 1964 and the IBM 360 Computer and EBCDIC code.

The PDP-1 was released in December 1959. The first edition of the 7-Bit ASCII character set was published in 1963. While IBM devised 8-Bit EBCDIC in 1963 and 1964. Therefore it is not surprising that DEC’s PDP-1 supported multiple character sets that would require conversions when manipulating text.

Papertape Codes

The PDP-1 supported a binary plus a character coding standards for papertape.

Words

The PDP-1 is a fixed sized, 18-Bit, digital computer which means the central processor and memory operate and store binary information in 18-bits. By definition, the word size of the PDP-1 is 18-Bits. The numerical values that can be stored will range from 0 to 262,143. The prefix 0b indicates the numbers are to be interpreted as binary numbers.

0b000000000000000000 to 0b111111111111111111

From Zero (0) to the highest 18-Bit number of all Ones (1) is 262,143 decimal.

The most significant bit is Bit-0 while Bit-17 will be the least significant bit. Therefore the number is interpreted from right to left.

Octal Number System

With a word size of 18-Bits and a character size of six bits it is convenint to use 3-Bit Octal numbers to convert long binary strings into a format human minds find more manageable. The prefix 0o indicates a number is to be interpreted as an Octal number. Therefore 0b111111111111111111 become 0o777777

Interpreting these 18-Bit binary numbers was never going to be practical for humans. To convert this binary number Digital Equipment Corporation (DEC) selected the octal number system.

An 18-Bit binary word such as 0b001010011100101110 can be logically sub-divided into groups of 3-Bits to ease the conversion to Octal. An 18-Bit is not so conveniently sub-divided into Hex with 4.5 Hex groups of Bits.

On the PDP-1 Consoles there are markings that divide the 18 switches and lamps into groups of three to enable easier Binary/Octal number conversions.

Positive and Negative Numbers

To represent both positive and negative numbers in an 18‑Bit word. Bit-0 becomes a sign bit.

• For Bit-0 as the sign bit set to ZERO (0) then the Bits-1:17 contains the magnitude of a positive number.
• For Bit-0 as the sign bit set to ONE (1) then the Bits-1:17 contains the magnitude of a negative number.

PDP-1 Binary Arithmetic

The PDP-1 binary arithmetic is based on Bit-0 as the sign bit and Bits‑1:17 are magnitude bits. Bit‑1 being the most significant and Bit-17 being the least significant. With Negative numbers represented by the one's complement of the positive numbers. In One's Complement arithmetic addition, subtraction, multiplication, and division of binary numbers is performed in accordance with the common rules of binary arithmetic. Negative numbers are represented as the complement of positive numbers, and subtraction is achieved by complement addition.

Complements

Just to complicate the issue there are two common representations for a fixed length. negative interger.

One's Complement Arithmetic

Assume Bit-0, the most significant Bit in the following example is the sign Bit. To convert the positive number three (3) such as 0b00011 into the One's Complement, negative number three (-3) all the bits are inverted i.e. the complement of 0b00011 is 0b11100. In this instance the sign Bit is ONE (1) indicating this is a negative number and the Bits‑1:4 are the magnitude bits. If we add +3 to -3 the reasonable expectation is the answer of zero (0).

By definition, a One's Complement, negative number is created by inverting/complementing all bits. The complement of Zero (0) 0b000000 is 0b111111 therefore the complement of zero has the sign bit set to One (1) which indicates -zero. As can be seen in the example above the result of -3+3 is -zero (-0).

Having to evaluate the results of arithmetic calculations which may produce a +zero or -zero result is a complication with One's Complement. The PDP-1 addresses this complication by automatically converting -0 to +0 with some arithmetic operations.

Two's Complement Arithematic

Representation of negative values for Two's Complement arithmetic is slightly different from that within One's Complement arithmetic. For One's Complement of a number, the complement of the absolute positive value is where all ones are replaced by zeros and all zeros are replaced by ones. In this case every positive number has an equivalent negative number. For Two's Complement of a number is equal to the One's Complement of the positive value plus one (1). In One's Complement arithmetic a carry from Bit-0 (the sign bit and most significant bit) is added to the least significant bit in an end-around carry. In Two's Complement arithmetic a carry from the sign bit complements the link (a carry would set the link to 1 if it were properly cleared before the operation), and there is no end-around carry.

A One's Complement representation of a negative number is always one less than the Two's Complement representation of the same number. Differences between one's and two's complement representations are illustrated below.

To simplify this situation some arithmetic instructions will automatically convert a result that is a negative zero (0o777777) into a positive zero (0o000000). Another issue that needs to be taken into account is overflow. A simple example is the addition of two (2) positive number e.g. 0o200000 plus 0o200000. The result is 0o400000 which has Bit-0 set i.e. a negative number. If an operation will result in an operation causing an unintended change of sign some PDP-1 instructions (i.e. arithmetic) will automatically set an overflow bit that can be tested.

One’s Complement Addition

The addition of a number contained in a core memory location and the number contained in the accumulator is performed directly by using the add Y instruction, assuming that the binary point is in the same position and that both numbers are properly represented in the appropriate One’s Complement arithmetic. Addition can be performed without regard for the sign of either the augend or the addend. Overflow is possible, in which case the result will have an incorrect sign, although the 17 least significant bits will be correct. Following the addition a test for overflow can be made by using the szo instruction.

One’s Complement Subtraction

Subtraction is performed by complementing the subtrahend and adding the minuend. As in addition, if both numbers are represented by their One’s Compliment, subtraction can be performed without regard for the sign of either number. Assuming that both numbers are stored in core memory, a routine to find the value of A-B follows:-

Processor Instructions

The majority of processor instructions have the following format:-

• Bit-0:4 defines the instruction code.
• Bit-5 is the indirect address bit. The function of this bit will be explained in the section on Memory.
• Bit-6:17 contains a 12-Bit memory address. This number of bits is sufficient to address 4,096 words of memory which is size of one memory module.

Needless to say there are a minority of processor instructions that are the exception and do not follow this format.

12-Bit Address Range

The processor instruction’s 12-bit addresses (4,096 address range) in Octal:-

This range is sufficient to address all of Memory Module 0.

Memory Module 16-bit Address Ranges

The PiPD-1 is configured with the PDP-1 maximum configuration of 16 memory module which requires a 16-Bit memory address to access all the available memory.

Translation of 12-Bit addresses to 16-Bit addresses

To construct a 16-bit address the Processor Instruction’s 12-Bit, Memory Address field provides Bit-6 through to Bit-17. The Program Counter provides Bit-2 through to Bit-5 which completes construction of a 16-Bit address.

An example calculation that forms a 16-Bit address.

'Normal' Memory Mode

Core memory modules in the early PDP-1 systems wre limited to 4,096 Words.

In ‘Normal’ memory mode if the 12-Bit portion of the memory address increments then the overflow does not increment the PC’s address component. In effect the 12-Bit memory address resets to 0o000000.

Computer Instructions

There are multiple ways of loading programs into a PDP-1 and the PiDP-1. For an introduction to PDP-1 programming only the the Console switches and lamps (i.e. Light Emitting Diodes - LEDs) wiil be used. These simple demonstration programs will be using the PiDP-1 Rack version’s Console Switches and LEDs. This is equally applicable to the standalone Console versions and the PC simulator without Blinkenlights

Machine Code

The PDP-1 is a binary digital computer with 18-Bit instructions. The Central Processor interprets binary numbers to execute the instructions of a program loaded into the computer’s memory. A valid Central Processor 18-Bit binary instruction is:-

Although the computer is executing binary it will be presented here in Octal for convenience. Therefore the computer machine code instruction above presented in Octal is:-
0o760000

Mnemonics

The presentation of PDP-1 machine code in Octal is a significant advance over the Binary but it does not convey to us how the computer will interpret instructions. Therefore three letter mnemonic codes were assigned for each machine instruction. In the case of 0o760000 the mnemonic is
nop
which is the simplest instruction for the PDP-1 as it is interpreted as no operation is to be performed by this instruction. The mnemonics may be written in lowercase nop or uppercase NOP.

Oddities

There can be multiple mnemonics that appear to provide duplicate functionality. For example, there can be three mnemonics to print a line on a line printer. As different models of line printer were introduced over the years. There was no set standard for interfaces and control logic therefore multiple sets of three mnemonics were created describing common line printer functions. Without readily providing sufficient information to identify which mnemonics were appropriate for which line printer. A rare issue of clashing I/O addresses could force a peripheral to be installed with a non-standard IOT address and that could force a mnemonic into supporting multiple machine codes.

Operate Group Event Table

This table indicates the order in which the instructions in the Operate Group are executed. For completeness, all the instructions in this group have been listed. Note that execution of the instructions lai, lia, and swp are completed in the next cycle, i.e., simultaneously with the execution of the next instruction. In other words the results for these operations do not become available or displayed at the completion of these instructions and before the next instruction is executed. When single stepping through code or program it may appear there is a logic error in your program or the machine. This is an incorrect assumption and the correct result will become available for the processor before it can cause an actual error

Every instruction requires multiple processor clock cycles to complete. A limited number of the processor clock cycles are listed as the Event Time in the table below. These processor clock cycles should not be confused with other clocks a PDP-1 system could have installed e.g. Real Time Clock. The action performed by the PDP-1 Processor's logic is listed in the Action column.

Understanding the contents of the following table is not required, it is only to demonstrate the results of a very limited number of instructions where results arrive later than expected.

PDP-1 Internal Registers

The registers with uppercase names such as PROGRAM COUNTER are shown on the diagram immediately below and their contents will be displayed on the PiDP-1 Console. A crude outline of how the PDP-1 computer executes one instruction is:-

1. The contents of the PROGRAM COUNTER register are copied to the MEMORY ADDRESS register.
2. MEMORY ADDRESS register contents address a location in the CORE MEMORY.
3. Contents of CORE MEMORY is read and 18-Bits are transferred to the MEMORY BUFFER register.
4. 5-Bits of the MEMORY BUFFER are copied to the INSTRUCTION register.
5. Contents of INSTRUCTION register is decoded by CONTROL as a machine code instruction.
6. The CONTROL executes the machine instruction and updates the PROGRAM COUNTER for the location in CORE MEMORY of the next machine code instruction.

"Control executes the machine instruction" is hiding the real complexiuty of the instruction.

PiDP-1 Console

PROGRAM COUNTER Display

The PROGRAM COUNTER provides the 12-Bit address of the next instruction to be executed. This 12‑Bit field will address 4,096 words of memory.

MEMORY ADDRESS Display

Displays 12 or 16 bits which represent the address of the instruction being executed (during cycle 0) or the address of the operand (in succeeding cycles).

EXTENSION Displays

The Extension Fields for the Program Counter and Memory Address Registers provide the additional 4-Bits to extend the 12-Bit memory addresses to 16-Bits to address all of main memory of XXX Words. As system memory was expanded in 4K word extensions (Type 12 Memory of 4,096 words) this reflected the number of the memory module being addressed.

This introduction to programming the PiDP-1 Rack Version will start with loading the Expensive Typewriter (ET) program using a configured Raspberry Pi. Refer to the PDP-1 Replica information on the Obsolescence Guaranteed website for the Build and Software Installation instructions or refer to the book PiDP-1, A Programmed Data Processor, by Andrew Barron, ISBN 9798173339805.

Cold Start Details – Read In Mode

This is just a simplified version of the starting instructions to have the PiDP-1 system in a known state. This procedure is not appropriate for restarting a program as there is no need to shutdown the system to restart the PDP-1 emulation. As this is a cold starting procedure the Raspberry Pi is not active.

1. PiDP-1 Console's SINGLE STEP and SINGLE INST. toggle switches off i.e. Actuators (Levers) of these switches to the right as shown in the Console photo above.
   This is a critical step as the Read In process will not function in single step mode of the PDP-1 emulation.
2. PiDP-1 Console's POWER switch On i.e. Actuator (Lever) of this switch to the left as shown in the Console photo above.
   This does not supply power to the Raspberry Pi, it just enables power to be supplied to the PiDP-1 Rack/Console when the Raspberry Pi has power and is awake i.e. not in sleep mode.
3. SENSE SWITCHES #1 and #6 on (i.e. Actuators up), all other SENSE SWITCHES off (i.e. Actuators down).
   This is the switch combination that selects the ET program. The default software currently available is listed in The DEC PDP-1 Manual, 2025 Online Edition, 1.3 Using the Sense Switches for quick boot options. Using this procedure it is possible to load various games, demonstrations and applications.
4. Switch Raspberry Pi power on and wait for the emulation to start.
   The small tact switch on the bottom panel, left side of the Console does not directly switch +5V but is a wake/sleep switch for the Raspberry Pi. At this point the appropriate software has been selected but not loaded into the PiDP-1 emulation.
5. SENSE SWITCHES #1 is now turned off (i.e. Actuator down) and SENSE SWITCHES #2 is now turned on (i.e. Actuator up).
   The other SENSE SWITCHES are not moved/change. What is not well documented is SENSE SWITCHES #1 Stop printout, punchout, searching or iteration. Effectively an emergency stop function. Inadvertently leaving SENSE SWITCHES #1 on will effectively disable the program.
6. Press READ IN switch to load ET.
7. After program load completes system the system should respond by typing ss2.

Instruction Code Examples

For an introduction to the PiDP-1 instruction set, the following is an example so limited this demonstration will use the Console for simplicity. The first step is to load three (3) words of 18-Bit data into the memory of the PiDP-1 system. To unclutter the data the Octal prefix will not be used and assume all the following are Octal numbers unless otherwise indicated.

When using the Console, the markings on the Console group the switches and indicators (LEDs) into 3-Bits. The following table provides the switch positions of Zero (0) is down and One i(1) is up for Octal Digits.

Program Entry

Memory

Ancient History

The initial F10-Data Sheet, May 1960 offered two memory sizes. 1024 Words (i.e. 10-Bits) and 4,096 words (i.e. 12-Bits) of memory. The Memory Field of PDP-1 instructions is 12-Bits so there was no requirement for any explicit instructions instructions to address more than 4,096 words. From the photographs this appears to be documenting a prototype PDP-1.

Some time later an Addendum was added to the F15-Handbook, May 1960 to expand memory up to a total of 8 memory modules for 32,768 words of memory. The Addendum added the implementation of a jfd instruction (i.e. Jump Field to connect the correct module). From the photographs this handbook appears to be based upon a prototype PDP-1.

F11A-Data Sheet, September 1961 appears to be documenting an early production system with updated Console and peripherals. The Data Sheet specified a maximum 8 of the Type 12 Memory Modules (4,096 Words) could be supported by the PDP-1.

A Type 13 Memory Field Control supported up to four Type 12 Memory Modules (16,384 words). While a Type 14 Memory Field Control supported up to eight Type 12 Memory Modules (32,768 words). The instruction set now included cdf (i.e. Change Data Field) and cfd (i.e. Change Fields) instructions. The two Console photographs did not include the Extend Switch and Extension Address labels. The F15B-Handbook, 1961 documented the F11A-Data Sheet.

F11B-Data Sheet, November 1963 documents the current Console layout with the Extend Switch and included the Memory Extension label. The instruction set now included Memory Extension Control eem (Enter Extend Mode) and lem (Leave Extend Mode) instructions. The cdf and cfd instructions were no longer included on the data sheet. These instructions should not be used in current programs but may appear in very old programs.

The F15C-Handbook, June 1963 documented the F11B-Data Sheet and included details of the Type 15 Memory Control that could support 16 of the Type 12 memory Modules for 65,536 words of memory. The cdf and cfd instructions were no longer included in the handbook. The PDP-1D Approved Options, October 1963 listed a Type 170 Memory Module of up to 16K words with a Type 121 Memory Control.

Skip Group

The intent of any skip instruction can be reversed by making Bit-5 equal to ONE.

Operate Group

This is a micro program set of instructions. Thus cla + cli + clf = 764207

In-Out Transfer Group (Basic List)

The number of variations in this group may be greatly increased for optional or special in-out equipment.

Shift Rotate Group

Shift is an arithmetic operation. The sign bit is left unchanged and vacated bits are filled with the sign. Rotate is a logical operation and cycles the bits (including sign) in a closed ring. The number of steps is the number of ONE's in bits 9-17 of the instruction (9 max).

References

Handbooks

Hardware

PDP-1D Approved Options1, October 1963PDP-1 Option List2, 1963Sequence Break System Technical Notes3, March 2023C-100 System Modules4, 1968F-18 PDP-1 Installation Manual5, May 1964H-23 Type 23 Parallel Drum Instruction Manual6, July 1964H-24 Type 24 Serial Drum Instruction Manual7, November 1965F-15(30E) Type 30 Precision CRT Display8, 1963Type 33 Digital Symbol Generator1, 1964PDP-9 Type 34H Oscilloscope Display, Instruction Manual2, July 1968Type 50/51/52 Magnetic Tape Equipment3, 1963H-340 Type 340 Precision Incremental CRT Display4, November 1964Type 550 Microtape Manual (Preliminary)5Type 550 DECtape Manual6Type 630 Data Communications System7, April 1964RAND Tablet8, November 1967

Input-Output

F-25 Input-Output Systems Manual9, 1960Programming Aids10, November 1963

Instruction Set

Architectural Evolution in DEC’s 18-Bit Computers11, by Bob Supnik, February 2016BBN Report No. 1217, Hospital Computer Project, Memorandum Number Six-A, Hardware Status Report, January 1965 Index Register and Micro-Program Instruction Class12, June 1968F-36BP MACRO Assembly Program For Programmed Data Processor-113, 1962

Aperture Cards

Maintenance

F-17 Programmed Data Processor-1 Maintenance Manual22, 1962F-47 Programmed Data Processor-4 Maintenance Manual23, 1962F-57 Programmed Data Processor-5 Maintenance Manual24, 1964